This invention relates generally to the computer-aided design of electronic circuits and, more specifically, to a method and apparatus for conforming such a circuit to given performance criteria (such as load and timing requirements specified by a user) by replacing standard cells representative of the components in the circuit with other standard cells from a standard cell library in order to improve the performance of that circuit. It is especially useful in the design of very large scale integrated (VLSI) microprocessor circuits.
A typical structured VLSI microprocessor design cycle consists of five stages: (1) architecture and instruction set design; (2) micro-architecture design and functional model validation; (3) logic design and schematic capture; (4) circuit design; and (5) physical layout. These stages are described below. It is to stage 4 that the present invention is directed.
Stage 1: During the architecture and instruction set design stage, a new microprocessor architecture is designed either to overcome performance problems in previous designs or to solve, using hardware, problems which have not been solved hitherto.
For instance, in reduced instruction set computing (RISC) microprocessor architectures, which are founded on the premise that a smaller instruction set allows a faster and more efficient design, an instruction set is designed so that one may solve problems in the shortest possible time using the smallest possible set of instructions.
During architecture design, one insures that the design is feasible and that no unreasonable assumptions are being made at this stage. The end product is a set of specifications that the final product must meet, as well as a set of assumptions made in creating this set of specifications.
Stage 2: Once the architecture and instruction set are designed, the designer validates them by building a behavioral model of the circuit which will implement this architecture. The behavioral model of the circuit describes its function by using equations to relate inputs to outputs. This will typically be done using a program such as Lsim, which is a logical simulation program from Silicon Compiler Systems. The behavioral model is tested using the Lsim program.
The initial set of specifications is decomposed into a set of blocks and sub-blocks in order to divide the design problem into a set of smaller design problems. An attempt is made to insure that these blocks correspond to blocks of logic on the final chip. A well-defined microarchitecture results from this stage--in which all internal registers, clock signals and their phase relationships, etc., are specified.
Stage 3: Logic design and circuit schematic capture follows functional model validation. As a result of this stage, the blocks in the circuit are defined by logic equations, state diagrams, and timing and sequencing information. That is, when the designer has determined that the behavioral model of the circuit meets the desired specifications, then the designer creates a schematic block diagram of the circuit, where each block includes one or more standard cells which are in a standard cell library. A standard cell library is a collection of commonly-used logic blocks which have been designed as transistor level circuits and which have been simulated in order to determine their operating characteristics and parameter values. The "standard cell" stored in memory is a representation of the characteristics of the component represented by a block of the block diagram.
A netlist (short for "network list") describing the connectivity of the circuit is also generated from this stage. A netlist is an ASCII table which lists all of the blocks in the circuit along with their corresponding inputs and outputs. Hence, information about the connections between the blocks in the circuit is also present in the netlist.
Stage 4: The next stage is the circuit design stage. During circuit design, logic blocks are replaced with standard cells from the standard cell library. The logic blocks in the circuit are then optimized in order to maximize speed and minimize circuit area and power dissipation, while maintaining adequate noise margins. All timing specifications must be met during circuit design.
Stage 5: Once the circuit has been designed, a physical layout is generated. At this point, the designer lays out each layer of the chip, including leaf level cells, power, ground and control signals.